`timescale 1ns/10ps
module par_ser_test;
  reg rst,clk,en;
  reg [7:0] din;
  wire dout;
  par_ser u1(rst,clk,dout,din,en);
  always #50 clk=~clk;
  initial
  begin
  clk=0; rst=0;
  #100 rst=1;
  #100 rst=1;en=1; din=8'b10010111;
  #100 rst=1; en=0; 
  #100 rst=1; en=0;
  #100 rst=1; en=0;
  #100 rst=1; en=0;
  #100 rst=1; en=0;
  #100 rst=1; en=0;
  #100 rst=1; en=0;
  #100 rst=1; en=0;
  #100 rst=1; en=1; din=8'b10010011;
  #100 rst=1; en=0;
  #100 rst=1; en=0;
  #100 rst=1; en=0;
  #100 rst=1; en=0;
  #100 rst=1; en=0;
  #100 rst=1; en=0;
  #100 rst=1; en=0;
  #100 rst=1; en=0;
  #300 $stop;
end

initial $monitor($time, , ,"clk=%b rst=%b en=%b din=%b dout=%b",clk,rst,en,din,dout);
endmodule